Electronic counter



June 12, 1962 R, A. HEMPEL 3,038,658

ELECTRONIC COUNTER Filed Sept. lll 1956 4 Sheets-Sheet l 62 Jes 72 ne 80 Je4 fsa 9e loo -190 INVENToR. ROY A. HE MPEL IWA/MM. 0M

ATTORNEY `lune 12, 1962 Filed Sept. ll. 1956 R. A. HEM PEL 3,038,658

ELECTRONIC COUNTER 4 Sheets-Sheet 2 82 /78 9o /85 98J /94 84 92 /oo- T INVENToR.

ROY A; HE/VPEL Hwa. MM

ATTORNEY June 12, 1962 Filed Sept. ll, 1956 SEMI R. A. HEM PEL ELECTRONIC COUNTER 4 Sheets-Sheet 3 18o @162 @164 @,166 @168 @17o @172 @174 @176 @178 Q9/ Fig 5 8 16/ 6.2 174/o ,S2/78 ,SQ/86 f9/94 Z68 Z76 284 292 Z10o \142 1144 \146 H48 15o LAMP COUNT 162 164 166 168 17o 172 174 176 178 18o o 83 oN 58 71 46 71 46 71 46 71 46 1 58 83 ON 46 71 46 71 46y 71 46 71 2 71 46 83 0N 58 71 46 71 46 71 46 3 46 71 58 83 oN 46 71 46 71 46 71 4 71 46 71 46 83o1\1 58 71 46 71 46 5 46 71 46 71 58 83o1\1 46 71 46 71 6 71 46 71 46 71 46 83o1\1 58 71 46 7 46 71 46 71 46 71 58 l 83o1\1 46 71 8 71 46 71 46 71 46 71 46 83o1\1 58 9 46 71 46 71 46 71 46 71 58 83 oN 1o 83o1\1 58 71 46 71 46 71 46 71 46 l IN1/15111701@ F1 g. 6 6 ROY A. HEMPEL BY /M a. 0M

ATTORNEY June 12, 1962 R. A. HEMPEL 3,038,658

ELECTRONIC COUNTER Filed sept. 11. 195e 4 sheets-sheet 4 COUNT PinO Pin! Pn2 Pin3 Pn4 Pn5 Pn Pin'l' Pin@l PinQ 9 ROY A. HEMPEL ATTORNEY United States Patent 3,038,658 ELECTRONIC COUNTER Roy A. Hempel, Cleveland, Ohio, assignor to Robotomics Enterprises, Inc., Phoenix, Ariz., a corporation Filed Sept. 11, 1956, Ser. No. 609,131 Claims. (Cl. 23S- 92) This invention relates to an electronic device and more particularly to an electronic counter capable of determining and indicating the number of electronic impulses of a predetermined polarity applied thereto.

Broadly, this invention comprehends the provision of a flip-flop multivibrator or binary circuit `for receiving incom-ing pulses to be counted and comprising among other circuit elements, two, three element semi-conductor devices having two conditions of stable equilibrium wherein either one of the semi-conductor devices is conducting and the other is non-conducting and providing a square wave in the output thereof for application to a quinary circuit comprising ve, three element semi-conductor devices having i'ive conditions of stable equilibrium wherein one semi-conductor device is non-conducting and the others are conducting to provide output signals. The quinary circuit is responsive to preferably the trailing edge of the mentioned square wave to shift from one condition of equilibrium to the next. Appropriate visual and electrical indicating means as, for example, suitable neon lamps are provided for indicating the number of pulses received in the counter input circuit.

In many industrial and military applications it is highly desirable and at times imperative that electronic counters be light in weight and occupy a minimum of space. As a consequence, counters have been provided that incorporate three electrode semi-conductor amplifiers cornmonly called transistors to overcome the undesirable `aspects of comparable electron tube circuits necessitating larger, heavier and more costly components. This inven tion incorporates the mentioned semiconductor devices for size and weight considerations and further incorporates a novel and more efficient circuit to further reduce the size and weight thereof.

Accordingly, it is an object of this invention to provide a novel electronic counter circuit that is light in weight, simple, compact, rugged, low-powered, eflicient and effective in accomplishing the purposes for which designed.

It is a further object of this invention to provide a novel multivibrator circuit of the bisable type having an increased frequency response.

It is `a `further object of this invention to provide an electronic counter circuit having a novel quinary circuit with ve conditions of stable equilibrium and being responsive to successive pulses of a predetermined polarity to successively alter the conditions of equilibrium of said circuit in an orderly sequence.

It is a further object of this invention to provide an electronic counter incorporating a novel visual indication of the count of said circuit.

It is a further object of this invention to provide an electronic counter incorporating novel means of electrically indicating the number of count reived thereby.

Other objects and advantages of this invention will become apparent from a more detailed description of the invention taken with the accompanying drawings in which:

FIGURE l illustrates an over-all counter circuit incorporated in this invention,

FIGURE 2 illustrates in a more graphical manner the quinary circuit of this invention,

FIGURE 3 illustrates la portion of the circuit of the invention facilitating a determination of potentials in the circuit,

FIGURE 4 illustrates a table of values of potentials of points in the circuit of FIGURE 3 for various stages of operation thereof,

FIGURE 5 illustrates a portion of the circuit of the invention facilitating a determination of potentials of points in the circuit,

FIGURE 6 illustrates la table of values of potentials of points in the circuit of FIGURE 5 for various stages of operation thereof,

FIGURE 7 illustrates a portion of the circuit of this invention facilitating a determination of potentials in the circuit,

FIGURE 8 illustrates `a table of values of potentials in the circuit of FIGURE 7 for various stages of operation thereof, and

FIGURE 9 illustrates schematically the relationship between the neon lamp indicators and the binary and quinary circuits.

Referring now more particularly to FIGURES l and 2 of the drawings, 10l represents generally the binary circuit of this invention having a first semi-conductor device 12 comprising a base preferably of N-type semi-conducting material 14, an emitter 1.6 and a collector 1'8 and` a second semi-conductor device 2li having a base preferably of Ntype semi-conducting material 22, an emitter 24 and a collector 26. The semi-conducting devices 12 and 20 are interconnected with passive circuit elements in a manner so as to provide a flip-flop or direct coupled multivibrator circuit. Base 14 is connected to collector 26 through a resistor 2S having a capacitor 30 in shunt therewith and base 22 is connected to collector 13 through a resistor 32 having a capacitor 34 in shunt therewith. A suitable load resistor 36, a resistor 39 and a potentiometer 38 for adjusting the magnitude applied to subsequent circuit elemen'ts are serially connected between collectors 18 and 26 and the junction of resistor 36 and potentiometer 38 is connected to an adjustable potentiometer 42 in series with a resistor 43 for connection to emitters of the quinary circuit to be described.

It is noted that under normal conditions of operation of the circuit of this invention, quinary circuit 60 requires somewhat greater power for operation thereof than binary circuit 10 and further requires a greater current. Accordingly, current in addition to that supplied through binary 10 is provided through resistor 40 connected to binary 60 between the potential source B-I- and quinary circuit 60 in parallel with binary circuit 10.

An input terminal 44 for receiving incoming signals is connected to base 14 through a capacitor 46 serially connected with a unidirectional diode 48 and to base 22 through a capacitor Sti serially connected with la unidirectional diode 52. The junction `of capacitor 46 and diode 48 is directly connected to base 22 `and the junction of capacitor 50 and diode 52 is direct-ly connected to base 14. Bases 14 and 22 are cross-coupled to respective collectors 26 and 18 through parallel resistor-capacitor combinations 28--30 and 32-34, respectively, to provide a direct coupled bistable multivibrator circuit. It is to he observed that diodes 48 and 52 may be considered as additions to a multivibrator circuit having an input connection to bases 14 and 22 through capacitors 5G and 46, respectively. According to a feature of the invention, diodes 48 and 52 facilitate an increased frequency response of binary circuit 10` of the counter over the same circuit without diodes 48 and S2. It is vfurther to be noted that according to the invention, other 'impedance elements such as resistors may be substituted for diodes 4S and 52 but that circuit 10 has a higher frequency response with unilateral rather than bilateral elements so disposed.

A suitable source of B-lpotential (not shown), positive with respect to bases 14 and 22 is applied to emitters 16 and 24. I

The parameters of binary circuit are so proportioned lthat upon the application of the emitter voltage, the current passing from emitter to collector in one of the semi-conductor devices '12 or 20 is greater than that in the other. In a manner well known, a cumulative action occurs, resulting in a heavy conduction in one semiconductor device and a very small conduction in the other. A bias voltage developed at a collector of the heavily conducting semi-conductor is applied to the base of the other semi-conductor in such polarity as to render the non-conducting semi-conductor conducting and the other conducting semiconductor cut-off in the absence of any extraneous influence.

Negative pulses received at input terminal 44 and applied to respective bases 14 `and 22 aifect only the nonconducting semiconductor wherein an instantaneous 'How of current occurs in the collector circuit which causes a positive pulse to be engendered as a result thereof across its collector load circuit and such positive pulse to be applied to the base of the previously conducting semi-conductor to lessen its collector current flow. As a consequence a negative pulse is engendered in the collector load circuit of such previously conducting semiconductor and is applied to the base of the previously non-conducting semi-conductor to further increase the flow therein. A repetitive and cumulative action, as described, of short time duration recurs many times and results in a new equilibrium wherein the previously conducting semi-conductor is rendered non-conducting and the previously non-conducting semi-conductor is conducting heavily. In response to a second negative pulse applied to the bases of the semi-conductors, a chain of similar events follows causing a shift back in the equilibrium of the circuit wherein the originally conducting semi-conductor is again conducting and the originally non-conducting semi-conductor is rendered non-conducting. Accordingly, the binary circuit 10 is responsive to input pulses applied thereto to shift the condition of equilibrium therein and to complete a cycle off shifts of equilibrium in response to every two input pulses.

Each time semi-conductor shifts from a state of conduction to non-conduction, a negative pulse generated in the collector load circuit thereof is applied to the quinary circuit 60, to be described, as the trailing edge of -a square wave. iIt is obvious, therefore, that every second negative pulse applied to input terminal 44 is effective to provide a single negative pulse in the output of binary circuit 10.

Quinary circuit 60 as illustrated in FIGURE l, and more graphically in #FIGURE 2 comprises ve semiconductor devices 62, 70, 78, 86 and 94, preferably of the PNP-type interconnected in a manner to be described. Semiconductor delvice 62 comprises a base 64, an emitter 66 and a collector 68. Semi-conductor devices 70, 78, 86 and 94 are entirely similar lto device 62 and include respective bases 72, 80, 88 and 96; respective emitters 74, 82, 90 and 98 and respective collectors 76, 84, 92 and 100. Bases 64, 72, 80, 83 and 96 are coupled to collector 26 in the binary circuit through respective capacitors 63, 71, 79, 87 and 95, each having one terminal connected to respective bases of the semi-conductors and the other terminals joined and connected to the movable arm of potentiometer 3S. Collector 68 of semi-conductor 62 is coupled to base 72 through a parallel resistorcapacitor combination 102-104 and is coupled to bases 80, 88 and 96 through resistors 106, 108 and 110, respectively. Collector 76 of semi-conductor 70 is coupled to base 80 through a parallel resistor-capacitor combination 112-114 and to bases 64, 88 and 96 through resistors 116, 118 and 120, respectively. Collector 84 of semiconductor 78 is coupled to base 88 through parallel resistor-capacitor combination 122-124 and to bas-es 96, 64 and 72 through resistors 126, 128 and 130, respectively. Collector 92 is coupled to base 96 through parallel resistor-capacitor combination 132-134 and to bases 64, 72 and 80 through resistors 136, 138 and 140, respectively. Collector is coupled to base 64 through a parallel resistor-capacitor combination 141- 143 and to bases 72, 80 and 88 through respective resistors 145, 147 Iand 149, respectively. Suitable load resistors 142, 144, 146, 148 and 150 are provided between each of the collectors 68, 76, 84, 92 and 100 and ground. Diodes 182, 184, 186, 188 and 190 are connected between bases of the semi-conductors for a purpose to be explained.

A visual indicator circuit is provided for visually indicating at any instant of time the number of counts received by the counter. Circuit 160 comprises a series of neon lamps 162, 164, 166, 168, 170, 172, 174, 176, 178 and 130, each being responsive to a predetermined value of potential in the output circuit of an associated semi-conductor to lire and light.

The collectors 68, 76, 84, 92 and 100 of the semiconductors are preferably connected to rst electrodes of respective pairs of neon lamps 162-164, 1664-168, -172, 174-176 and 178-180. The second electrodes of each of the neon lamps 162, 166, 170, 174 and 178 are electrically joined and connected through resistor 183 to collector electrode 18 in the binary circuit described and the second electrodes of each of neon lamps 164, 168, 172 and 180 are electrically joined and connected through resistor 194 to collector 26 in the binary circuit.

Collector 18 in binary circuit 10 is connected to rst electrodes of neon lamps 164, 16S, 172, 176 and 180 through respective pairs of serially connected pairs of parallel resistor-capacitor combinations 198-298, 199- 299; 202-302, 203-303; 206-306, 207-307; 210- 310, 211-311 and 214-314, 21S-315 and collector electrode 26 in binary circuit 10 is connected to second electrodes of neon lamps 164, 163, 172 and 180 through a resistor 194 and to first electrodes on neon lamps 162, 166, 170, 174, and 178 through respective pairs of serially connected pairs of parallel resistor-capacitor combinations 196-296, 197-297; 200-300, 201-301; 204- 304, 205-305; 208-308, 209-309 and 212-312, 213-313. Capacitors 296 through 314 are provided to improve the strength of the signal output of the counter circuit at high frequencies `and have values depending on the physical layout of the counter circuit and concomitant inter-circuit electrical parameters.

By way of example only, specifications and values of circuit components, which may be used in this invention are as follows:

Semi-conductors 12, 20, 62, 70, 78, 86,

Resistors 102, 106, 108, 110, 112, 116, 118, 120, 122, 126, 128, 130, 132, 136, 138, 140, 141,

145, 147, 149 ohrns 22,000 Resistors 142, 144, 146, 148 and 150 do- 4,700 Resistors 182 and 194 do 100,000 Resistors 1'36-205 megohms 2 Potentiometer 38 ohms 7,700 Diodes (all) 1N34 For a more detailed explanation of the operation of the invention, reference is had to FIGURES 3, 4, 5, 6, 7, 8 and 9.

FIGURE 3 illustrates portions of each of the binary and quinary circuits of FIGURE 1 and FIGURE 4 illustrates representative values of collector potentials with respect to ground, of the semi-conductors of the binary and quinary circuits, assuming the values of circuit parameters as set forth hereinabove. Further assuming a source of direct potential of 95 volts applied between emitters 16 and 24 and ground, an initial condition wherein semiconductors 12, 70, 78, 86 and 94 are conducting and therefore semi-conductors 22 and 62 are non-conducting, voltages appearing at the respective collectors of semiconductors 62, 70, 78, S6, 94, 12 and 20 are shown in the first row in the table in FIGURE 4 for the zero (0) count. It should be observed that the potential of collector 68 of semi-conductor 62, the only non-conducting semi-conductor of the quinary circuit is unique and that the potentials of each of the other collectors of the quinary circuit are equal in value.

As shown schematically in FIGURE 9, this invention comprises a binary circuit serially connected with a potential source, an adjustable potentiometer 42 and a quinary circuit and further having a neon indicator in series with an appropriate resistor in shunt with the adjustable resistor and quinary circuit. As a preliminary condition, potentiometer 42 is adjusted to provide an appropriate potential drop across the neon tube circuit to facilitate firing only in response to maximum potentials developed as set forth in the table of FIGURE 6.

Assuming now the application of an input pulse to terminal 44, it is noted that a change in the equilibrium of binary circuit 1t) occurs whereby semi-conductor 12 is cut-olf and semi-conductor 2t)` is rendered conducting. Consequently, the potentials at collectors 18 and 26 reverse as shown in FIGURE 4 for count 1. The potentials at collectors in quinary circuit 69, however, remain the same as for Zero count since a negative output pulse capable of affecting quinary 6G, is produced in binary 1t) only when semi-conductor 2G is rendered non-conducting after having previously been conducting.

In response to a second input pulse, the following sequence of events takes place: Semi-conductor 12 is rendered conducting and semi-conductor 20 is rendered nonconducting producing a negative pulse in the circuit of collector 26. The negative pulse so produced is applied to the bases of semi-conductors 62, 70, 78, S6 and 94 tending to initiate conduction in semi-conductor 62 and to increase conduction of the other semi-conductors in the quinary circuit. Semi-conductors 70, 78, S6 and 94, however, are conducting heavily and any increased conduction effected by such pulse in these semi-conductors is insignificant and ineffective in producing any direct results. Semi-conductor 62 on the other hand is rendered conducting whereby the collector potential thereof changes suddenly from l2 volts to 24 volts as observed in the table of `FIGURE 4. This potential change is applied to the bases of all other semi-conductors in the quinary circuit. However, since coupling between collector 68 and the next succeeding base in the quinary loop includes a parallel combination `o'f capacitor 104 and resistor 102 alfording a reduced impedance compared with that of resistors` 106, 108 and 110, to such pulse, only semi-conductor 70` is sufficiently affected to be rendered non-conducting and semi-conductors 78, 86, 94 and 62 remain conducting. It is to be understood that the count of quinary circuit 60 is determined by condensers 104, 114, 124, 134 and 143 and the count proceeds in a counter clockwise direction in gure of the drawings. The count could be reversed in direction by connecting condensers 104, 114, 124, 134 and 143 from the semi-conductor collectors to the bases of the semiconductors preceding the respective ones considered rather than to the bases succeeding the semi-conductors considered.

Reference to FIGURE 4 illustrates that in this state of operation, the potentials at collectors 18 land 26 with respect to ground yagain reverse and that the potential at collector 76 of semi-conductor 70 is unique at 12 volts 6 and that the potentials at collectors 84, 92, 16@ `and 68 are equal at 24 volts.

It is to be observed in FIGURE 4 that the voltages of collectors 18 and 26 of semi-conductors 12 and 20 in the binary circuit shift or reverse in response to each incoming negative pulse and that the potential of the lone conducting semi-conductor in the quinary circuit is unique with respect to all other collector potentials in the quinary circuit for two successive pulses of every ten applied to the input. Also, it is yto be observed that in response to each two incoming negative pulses, the semi-conductors in the quinary circuit are sequentially and uniquely rendered conducting.

In FIGURE 5 is shown a portion of the present counter circuit and in FIGURE 6` are values of certain potentials with respect to ground, of points in the circuit of FIGURE 5. The vertical columns represent potentials appearing in the circuit of FIGURE 5 across neon lamps and the rows represent such potentials at respective neon lamps for the respective number of pulses applied to the input of the circuit or in other words, the count number.

Assuming in the circuit of FIGURE 5 that no pulses have been applied to the input thereof, it is observed that with circuit elements of the value listed above, the collector potential of semi-conductor 12, which is conducting, is volts and the collector voltage of semi-conductor 62 i-s 12 volts. Since lneon lamp 162, representing Zero count, is connected across these collectors, the difference between the potentials at these collectors or 83 volts is impressed upon this lamp. Accordingly, lamp 162 is fired since the potential impressed thereon exceeds its firing potential. In a similar manner, potentials impressed upon neon tubes 164-180 are determined and listed for zero (O) count in the rst row of the table of FIGURE 6. The potential of collector 26 under such circumstances is 70 volts and the potential of each of collectors 76-106 is 24 volts and it is noted that the voltage of no neon lamp other than lamp 162 exceeds 71 volts. Accordingly, each lamp is off or not red.

It is next assumed that a single input pulse is applied to the circuit input, rendering semi-conductors 20, 70 78, 86 and 94 conducting and semi-conductors 12 and 62 cut-off in a manner explained hereinabove. It is readily understood that the maximum potential of 83 volts appears between collectors 26 and 68 and therefore across neon tube `164 to fire the same. Likewise it is observed that potentials of the remaining neon lamps are as listed in the table of FIGURE 6, and insufficient to re any of neon lamps 162 and 166-180. -In a similar manner it may be determined that a maximum potential of 83 volts appears across successive lamps 162-189v as successive impulses are received at terminal 44 and that corresponding to each impulse an individual neon la-mp has such maximum potential applied thereto -to fire the same and that all other neon lamps fail to fire because of insuicient applied potential. It is therefore clear that neon lamps 162--180 indicate the number of pulses less than ten applied to input terminal 44 according to the number of the neon lamp tired.

According to another feature of this invention, as electrical indication of the count received in the counter input may be obtained. To this end, signals facilitating such a determination are derived at ten output pins 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 shown more clearly in FIGURE 7 of the drawings. FIGURE 7 illustrates that portion of the circuit of FIGURE l including semi-conductors 12 and 20 of binary circuit 16 and semi-conductors 62--94 of quinary circuit 60 and various passive circuit elements associated therewith. It is noted that pin 0 is connected to the junction of a pair of resistors 196 and 197, the other ends of which are connected toi-respective` collectors 68- and 26. Accordingly, under operating conditions as assumed hereinabove, the potential of pin 0 is arithmetically determinable with the knowledge ofpotentials empirically determined Yat respective collectorsl in the counter circuit.

Under initial conditions wherein no input pulse has been received and semi-conductors 12 and 70-94 are conducting and semi-conductors 20 and 62 are non-conducting; the potential appearing at collector 26 is substantially 70 volts and that appearing at collector 68 is substantially 12 volts. Manifestly, a potential drop of 58 volts appears across resistors 196 and 197 whereby 29 volts appears from the junction thereof to the remote end of either. Consequently, pin assumes a potential which is the sum of that at collector 68 plus that across resi-Stor 196 equal to 12 plus 29 or 4l volts.

In a similar manner the potentials of points 2 to 9 may be determined for the zero count condition and in FIGURE 8 these potentials appear in the first row to indicate the zero (0) count. It is to be noted that the potential of any of pins 0 to 9 may be determined for any number of counts received by the counter circuit and that the potentials of each pin are indicated in the respective columns in the table in FIGURE 8. It is further to be noted that the potential for zero (0) count of pin 0 is a minimum with respect to the same pin for other counts and that the potential of each successive pin of pins 0 to 9 is a minimum `for the number of count equal to the number of the pin considered. Accordingly, the potentials of pins 0 to 9 may be applied to remote circuit means responsive to such minimum potentials to give a remote indication of the number of count received in the counter circuit of this invention.

In situations wherein it is desired to initiate some operation in response to a receipt of a predetermined number of counts in the present counter circuit, circuit means responsive to a minimum voltage as derivable at the pins 0 to 9 may be connected by a suitable selector switch to either one of pins 0 to 9 so as to be appropriately triggered and activated upon the receipt of the number of count desired. For example, assuming that it is desired to activate a circuit means (not shown) upon the receipt of the seventh count in the present counter, connection between pin 7 and such circuit means is appropriately made. In a manner explained hereinabove, pin 7 assumes a minimum potential upon the receipt of the seventh count in the counter input circuit. Accordingly, an appropriate signal is applied from pin 7 to the circuit means in response to the receipt of the seventh count.

As a further feature of the invention, provision is made for resetting the counter circuit to an initial condition wherein, of course, semi-conductors 12, 70, 78, 86 and 94 are rendered conducting and semi-conductors Z0 and 62 are rendered non-conducting or cut-off irrespective of the count indicated by the circuit. To this end, connection is made from reset pin 250 to base 14 of semi-conductor 12 in the binary circuit 10 and to collector 68 of semi-conductor 62 in quinary circuit 60 through serially connected capacitor-diode combination 252-254 and diode 256, respectively. Capacitor 252 serves as a low impedance to high frequency signals and serves to block direct current providing isolation between quinary and binary circuits while in operation. When it is desired to return the counter circuit -to its initial condition of operation a pulse of appropriate polarity and of any suitable duration and of suiiicient magnitude is applied to terminal 250 to be impressed upon base 14 and collector 68 as hereinabove set forth. As a consequence, semi-conductors 20 and 62 are rendered non-conducting whereby semiconductors 12, 70, 78, 86 and 94 are rendered conducting. The counter circuit is therefore adapted for further operation in the manner already explained.

A `suitable output teminal 350 is connected to collector 68 and it is understood that a single output pulse is engendered in response to every ten input pulses applied to input terminal 44. Pulses produced in output circuit 350 are adapted to be applied to further counter circuits for counting to sums greater than that enabled by the circuit of this invention.

It is noted that this invention incorporates as a feature thereof, diodes 48, 52 and 182---190` for improving the frequency response of the circuit. In a circuit according to this invention incorporating the diodes described, the frequency response of the binary circuit was increased from approximately kilocycles per second to approximately' 175 kilocycles per second and the frequency re- Sponse of the quinary circuit was increased from approximately 45 kilocycles per second to approximately 75 kilocycles per second, each figure representing an upper limit.

It is to be understood that preferably the transistors utilized in this invention are substantially uniform in all characteristics such as lbase and emitter resistance, gain, frequency response to provide a more balanced and accurate circuit. While the semi-conductors of this invention have been described as being of the PNP type, other semi-conductors such as NPN type may be used throughout provided the potential source designated B+ is reversed so as to provide volts negative with respect to ground at emitters 16 and 24.

While this invention has been described with reference to a certain specific embodiment thereof, it is understood that the same is susceptible to numerous modifications and variations without deviating or departing from the spirit or scope thereof.

I claim:

1. An electronic counter circuit comprising a first circuit including a pair of semi-conductor devices each having a base, an emitter and a collector, said pair of semiconductor devices being cross-coupled to provide a bistable binary circuit, a second circuit having five semiconductor devices each having a base, an emitter and a collector, the bases and collectors of the semi-conductor devices of said second circuit being cross-coupled to provide a quinary circuit having five conditions of stable equilibrium, the bases of said quinary circuit being coupled to a collector circuit of one of said pair of semi-conductor devices, said quinary circuit being responsive to the output pulses of said binary circuit to produce output pulses indicative with the output of said binary circuit of the count received by said counter circuit, a lamp indicator circuit having a plurality of lamps with opposite terminals coupled to collectors of devices in said binary and quinary circuits respectively and responsive to the outputs of said binary and said quinary circuits to visually indicate the number of pulses received by said counter circuit and an output pin for providing an output pulse in response to every ten input pulses received by said counter circuit.

2, An electronic counter circuit comprising a first circuit including a pair of semi-conductor devices each having a base, an emitter and a collector, a signal input circuit coupled to the bases of said pair of semi-conductor devices, the collectors and bases of said pair of semiconductor devices being cross-coupled to provide a bistable binary circuit responsive to every two input pulses applied to said bases to provide a single output pulse at the collector of one of said pair of semi-conductor devices, a second circuit including at least iive semi-conductor devices each having a base, an emitter and a collector, the bases of each of said semi-conductor devices in said second circuit being coupled to the collector of said one of said pair of semi-conductor devices, and each of the bases and collectors of said semi-conductor devices of said second circuit being cross-coupled to provide a multi-stable quinary circuit responsive to the output pulses of said binary circuit to produce a single output pulse for every five pulses applied to said quinary circuit, a visual indicator circuit including five pairs of lamps, each pair of lamps having first terminals connected to a collector of a semi-conductor in said quinary circuit and respective second terminals coupled to separate collectors of semi-conductor devices in said binary circuit, said visual indicator being responsive to potentials developed at respective collectors of said semi-conductors to sequentially and individually light said lamps in response to successive input pulses to said binary circuit.

c. 4 mi 3. An electronic counter circuit according to claim 2 additionally comprising an adjustable resistive means for controlling the responsiveness of said lamps.

4. An electronic counter circuit comprising a first circuit including a pair of semi-conductor devices and being cross-coupled to provide a bistable binary ci-rcuit responsive to two input pulses to provide a single output pulse, a quinary circuit including a further plurality of semiconductor devices each having a base and a collector, the collector of each of said further semi-conductor devices being coupled to a base of another of said further semi-conductor devices through a parallel connected resistor-capacitor combination and being coupled to a base of each of the other of said semi-conductor devices through a resistor, a Visual indicator including ten lamps each having a pair of terminals, a first terminal of each lamp being coupled to one of the collectors in said binary circuit and a second terminal of each lamp being coupled to one of the collectors in said quinary circuit, each lamp being coupled to a different combination of collectors, said lamps being responsive to output potentials of said binary and quinary circuits to provide an indication of the number of input pulses received by said binary circuit.

5. An electronic counter circuit comprising a first pair of semi-conductor devices being cross-coupled to provide a bistable binary circuit responsive to two input pulses to provide a single output pulse, a quinary circuit including third, fourth, fifth, sixth and seventh semi-conductor devices each having a base and a collector, the collectors of said third, fourth, fifth, sixth and seventh semiconductor devices being connected respectively, to the bases of said fourth, fifth, sixth, seventh and third semiconductor devices through parallel resistor-capacitor combinations and being resistively connected respectively, to the bases of said seventh, third, fourth, lifth and sixth semi-conductor devices, visual indicating means including five pairs of lamps, each pair of lamps having first electrodes connected to the collector of one of said semiconductor devices in said quinary circuit, and having second electrodes resistively coupled to respective semiconductor devices in said binary circuit whereby said indicator is responsive to potentials engendered in said binary and quinary circuits responsive to input pulses applied to said counter to sequentially and individually light said lamps to indicate the number of pulses received in said counter.

6. An electronic counter apparatus comprising a first circuit having a pair of semi-conductor devices each having a base and a collector intercoupled to form a circuit having two states of equilibrium in each of which one of said devices is in a unique condition of conduction, a second circuit having five semi-conductor devices, each having a base and a collector, the base of each device of said second circuit being coupled to the collector of each other device in said second circuit to form a circuit having live states of equilibrium in each of which one of said devices is in a unique condition of conduction, an indicator circuit including ten electrically responsive indicator elements each having a pair of electrodes, the collector of each device of said first circuit being directly coupled to a first electrode of a different live of said elements, the collector of each device of said second circuit being directly coupled to a different pair of said elements whereby only one of said elements is directly coupled across a pair of collectors of said respective circuits which are in a unique condition of conduction.

7. An electronic counter apparatus comprising a iirst circuit having a first plurality of active circuit devices each having a control electrode and a collector electrode, the control electrode of each device being directly coupled to the collector electrode of each other device of said first circuit to form a multistable circuit having said first plurality of states of stable equilibrium in each of which one of said devices is in a unique condition of conduction and the collector of said one device is at a unique` potential, a second circuit having a second plurality of active circuit devices each having a control electrode and a collector electrode, the control electrode of each device of said second circuit being directly coupled to the collector of each other device of said second circuit to a unique potential, a third plurality of electrically excit-` able indicator elements each having a first and a second electrode, the collector of each device of said first plurality being directly coupled to the first electrode of a different, equal group of said elements and the collector of each device of said second plurality being directly coupled to the second electrode of a different, equal group of said elements whereby only one element has applied there-across the potentials of collectors having unique potentials from said respective circuits.

8. An electronic appartaus comprising a binary circuit including a pair of semi-conductor devices each having a base, an emitter and a collector, the collector of each of said devices being directly and capacitively coupled to the base of the other of said devices, a quinary circuit including five semi-conductor devices each having a base, an emitter and a collector, the b-ase of each of said quinary circuit devices being directly coupled to the collector of each other device of said quinary circuit and capacitively coupled to the collector of only one of the other of said quinary circuit devices, the collector of each of said quinary circuit devices being capacitively coupled to only one of the other of said quinary circuit devices, the collectors of the devices of one of said circuits being directly coupled to the emitters of the devices of the other of said circuits, a plurality of indicator elements each having one terminal directly coupled to a collector of a device of said binary circuit and another terminal directly coupled to` a collector of a different device of said quinary circuit, another plurality of indicator elements each having one terminal directly coupled to a collector of the other device of said binary circuit and another terminal directly coupled to a collector of a different device of said quinary circuit whereby said indicator elements are sequentially energized in response to a succession of input pulses applied to the bases of one of said circuits.

9. An electronic counter apparatus comprising a first circuit including a pair of semi-conductor devices each having a base, an emitter and a collector, the bases and collectors of said devices being directly `and capacitively cross-coupled to form a bistable circuit having Ia pair of states of stable equilibrium in each of which the collector of one of said device is at a unique potential, a second circuit including live semi-conductor devices each having a base, an emitter and a collector, the base of each of said devices in said second circuit being directly coupled to the collector of each other device in said second circuit, and being capacitively coupled to the collector of one of the devices in said second circuit to form a multistable circuit having five states of stable equilibrium in each of which the collector of a different one of said devices in said second circuit is at said unique potential, means coupling the collector o f a device in one of said circuits to the bases of the other of said circuits, and adjustable resistor means directly intercoupling the collectors of one of said circuits with the emitters of the other of said circuits, a plurality of electrically responsive indicator elements each having a tirst and a second terminal, one-half of said indicator elements having their first terminals directly coupled to the collector of one of the devices of said first circuit and the other half of said elements having their first terminals directly coupled to the -collector of the other of the devices of said first circuit, different pairs of said elements having their second terminals directly coupled to a collector of a different device in said second circuit, whereby `a single one of said indicator elements is coupled across collectors of said circuits which have unique potentials thereat and said adjustable resistor is effective to control the energization o-f said apparatus in response to the application of a potential across the emitters of said one circuit and the collectors of the other of said circuits.

10. An electronic apparatus comprising a binary circuit including a pair of junction-type semi-conductor devices each having a base, an emitter and a collector, means directly and capacitively cross-coupling the bases and collectors of said binary circuit devices, a quinary circuit including live, junction-type semi-conductor devices each including a base, an emitter and a collector, the base of each quinary circuit device being directly coupled to the collector of each other quinary circuit device and capacitively coupled to the collector of only one other quinary circuit device, a plurality of electrically responsive indicator elements each having one terminal directly coupled to the collector of a binary circuit device and another terminal coupled to the collector of a quinary circuit device, adjustable resistor means interposed between the collectors of one of said circuits and the emitters of the other of said circuits whereby the current through said devices and the potentials at the collectors of said devices may be controlled in response to the application of a potential across the emitters of the devices of said one l2 of said circuits and the collectors of the devices of the other of said circuits to control the potentials applied to said indicator elements.

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